1. Field of the Invention
This invention relates to transistors. More particularly, this invention relates to junction field effect transistors (commonly known as JFETs) formed in integrated-circuit (IC) chips.
2. Description of the Prior Art
Junction field effect transistors have been in use for many years, and generally are considered advantageous because their high input impedance results in quite low current being drawn from the device supplying the input signal, and also because they have relatively low noise. Thus JFETs frequently are employed as the input stage of high-performance amplifiers. In such arrangements, the JFETs generally are integrated on an IC chip with conventional bipolar devices, for example, to form an operational amplifier.
Prior art JFET devices typically are formed in an epitaxial layer often grown over a buried collector diffused in a substrate. The JFET devices include two source/drain regions of conductivity type opposite to that of the epitaxial layer, and are connected by a channel region of that same opposite conductivity type. (The term "source/drain" is used to identify a region which can serve interchangeably either as a source or as a drain, depending upon the characteristics of an associated circuit.) Current flow through the channel is controlled by the potential of a gate region adjacent the channel. In the usual JFET, there will be both a top gate and a back gate, i.e. the regions just above and just below the channel.
The source/drain regions of a JFET ordinarily are formed by standard diffusion techniques. The channel however commonly and advantageously is formed by ion-implantation, in a region which lies a small distance below the surface of the IC chip. Just above the channel implant, there is an even shallower implant of opposite type, i.e. of the same conductivity type as the epitaxy. This latter implant is referred to as the shield layer, and serves to provide an electrostatic image for any charges exterior to the device which might otherwise find an image in the channel and thus affect the current flowing there. Such exterior charge can for example be from static, from sodium in an oxide layer, or from monolayers of polar molecules chemisorbed on the surface of the chip. The shield layer provides stability for the devce, and also constitutes the top gate for the JFET channel between the source/drain regions.
The top gate of a JFET device must be electrically connected to some controlled potential, or the device will be electrically unstable. If no such connection is made, the device will behave as though the stabilizing layer were not present. Making connection to the top gate in the normal fashion from above the chip, i.e. directly to the upper surface of the top gate, has however presented a problem due to the extreme shallowness of the shield and channel regions which in turn result from the use of ion-implantation. For example, if the commonly used contact metallurgies such as Aluminum are employed to make such direct connection to the top gate, it will be found that the metal tends to penetrate through the shallow top gate layer to the channel, causing a gate-to-channel short circuit.
To avoid that problem, the top gate conventionally is maintained at a controlled potential by connecting it to the back gate, and by directing the input signal to the back gate, thereby indirectly controlling the potential of the top gate. This top gate-to-back gate connection typically is made by a diffusion which extends from the upper surface of the semi-conductive body down through a small area of the channel region to the epitaxial layer. In such prior art devices, no electrical contact is made to the top gate from above that gate, and the two gates always are connected together.
With the top and back gates connected together as described above, the leakage current of the device will include contributions from both the top and back gates. The total leakage current in such case is relatively large, especially in view of the substantial effective area of the back gate. Such relatively large leakage current has detracted from the performance capabilities of prior art JFETs of the type described hereinabove.